# ===   Firmware version   ===
#The version item has been automatically generated assigned actually
#firmware version.
#
#WARNING: Don't change this Item. It could lead to unpredictable results!
#
#Item <<fw_ver>>: Firmware version
#            par1: [version]
#

fw_ver = "V2.19.2"


#############################################################################
###           Switch configuration file for NAT-MCH                       ###
#############################################################################
#
# NOTE: This configuration file can only be used for NAT-MCH Rev 2.1 or ewer
#
# * Common configuration file format is: parameter = value0, value1 ...
# * Each parameter/value(s) assignment has to be written into single line.
# * The line length is limited to CF_MAX_LINE_LEN (currently set to 1024)
# * It is application dependent whether a parameter takes values, if so the
#   delimiter '=' has to be used to separate the values from the parameter.
# * Multiple values have to be delimited by a ','.
# * Any number of values is allowed, but the number of values is limited by
#   the allowed line length.
# * Values must be integer numbers or strings.
# * Any number of blank characters (' ') can be inserted before, after and
#   between the parameter, values, delimiters and lines
# * '#' character is used for comments.
# * Any characters after a '#' in a line are ignored, i.e. '#' can also be
#   used after the parameter/value(s) assignment



#############################################################################
###                           Switch configuration                        ###
#############################################################################
#
#
# Driver type: Broadcom 5396
#


# ===   Device Location Identifier ===
#The following items point physical placing of some switch-device locating
#on the NAT-MCH board.
#
#
#WARNING: A mistaken change could lead to unpredictable results!
#
#Item <<mch_id>>: MAT-MCH ID (don't change)
#            par1: [0]
#
#Item <<mez_id>>: Mezzanine level
#            par1: [0|2]
#
#Item <<ins_id>>: Device ID of mezzanine level
#            par1: [0-8]
#


mch_id = 0
mez_id = 0
ins_id = 0





# ===   Port Based VLAN configuration   ===
#
#Item <<eth_pbvlan_ini>>:Port Based VLAN state
#             par_1: [0] - deactivated
#                    [1] - activated
#
#Item <<eth_pbvlan_encm>>: list of connections that are enabled (administrative up)
#     e.g eth_pbvlan_encm =AMC1/0, AMC1/1, AMC2/0, AMC2/1, AMC3/0
#
#
#Item <<eth_pbvlan_fwcm>>: Forwarding Map
#            par_1: source connections
#            par_(2 ..): Forwarding Map (list of AMC Ports)
#     e.g.: eth_pbvlan_fwcm =AMC1/0,	AMC1/1, AMC2/1, AMC3/1, AMC4/1
#

eth_pbvlan_ini  = 1

eth_pbvlan_fwcm =AMC1/0,	AMC2/0, AMC3/0, AMC4/0, AMC5/0, AMC6/0
eth_pbvlan_fwcm =AMC1/1,	
eth_pbvlan_fwcm =AMC2/0,	AMC1/0, AMC3/0, AMC4/0, AMC5/0, AMC6/0
eth_pbvlan_fwcm =AMC2/1,	
eth_pbvlan_fwcm =AMC3/0,	AMC1/0, AMC2/0, AMC4/0, AMC5/0, AMC6/0
eth_pbvlan_fwcm =AMC3/1,	
eth_pbvlan_fwcm =AMC4/0,	AMC1/0, AMC2/0, AMC3/0, AMC5/0, AMC6/0
eth_pbvlan_fwcm =AMC4/1,	
eth_pbvlan_fwcm =AMC5/0,	AMC1/0, AMC2/0, AMC3/0, AMC4/0, AMC6/0
eth_pbvlan_fwcm =AMC5/1,	
eth_pbvlan_fwcm =AMC6/0,	AMC1/0, AMC2/0, AMC3/0, AMC4/0, AMC5/0
eth_pbvlan_fwcm =AMC6/1,	
eth_pbvlan_fwcm =FRT_1,	CPU_1
eth_pbvlan_fwcm =FRT_2,	
eth_pbvlan_fwcm =UPDC_B,	CPU_1
eth_pbvlan_fwcm =RTM,	
eth_pbvlan_fwcm =CPU_1,	FRT_1, UPDC_B





# ===   802.1Q VLAN configuration   ===
#
#Item <<eth_802.1q_ini>>:  802.1Q VLAN state
#            par_1: [0] - deactivated
#                   [1] - activated
#
#Item <<802.1q_lrn>>: Learning mode
#            par_1: [0] - only use MAC for address learning
#                   [1] - use MAC and VLAN ID  for address learning
#
#Item <<eth_802.1q_m_cm>>: VLAN Membership Port Map
#            par_1: VLAN ID
#            par_(2 ..): [alias 1], .., [ alias n] -
#                        Membership Map(list of  AMC Ports)
#     e.g.: eth_802.1q_m_cm = 0100,	AMC1/0, AMC2/0
#
#Item <<eth_802.1q_u_cm>>: VLAN Untagging Port Map
#            par_1: VLAN ID
#            par_(2 ..): Utagging Map(List of AMC Ports, where frame is to
#                         be untagged )
#     e.g.: eth_802.1q_u_cm = 0100,      AMC1/0, AMC2/0
#
#Item <<eth_802.1q_dfl>>: 802.1Q Default Tag
#            par_1: [alias]Connection ID
#            par_2: 802.1Q Default VLAN ID
#            par_3: 802.1Q Default Priority
#     e.g.: eth_802.1q_dflt =   AMC1/0,  0001,  100
#

eth_802.1q_ini  = 0






# ===  MAC-Table Configuration   ===
#Item <<eth_mac_ageinit>>: Age Time of the MAC-Table
#            par_1: [0] - deactivated
#                   [1] - activated
#
#
#Item <<eth_mac_agetime>>: Age Time of the MAC-Table in seconds
#            par_1: - Time in seconds
#     e.g: eth_mac_agetime =    300
#
#
#Item <<eth_mac_ent_con>>: MAC-Table static entries
#            par_1: [xx:xx:xx:xx:xx:xx] - MAC Address
#            par_2: [xxxx] - VLAN ID(1-4094)
#            par_3: [xx] - Priority ID(0-7)
#            par_4: [alias] - AMC Port
#     e.g: eth_mac_ent_con =  00:13:22:33:44:55,  00100,  00, AMC3/0
#

eth_mac_ageinit =    1
eth_mac_agetime =    300





# ===  802.1x Configuration   ===
#
#Item <<eth_802.1x_ini>>: 802.1X Protocol state
#            par_1: [0] - deactivated
#                   [1] - activated
#
#Item <<eth_802.1x_dm>>: Dropping mode
#            par_1: [0] - drop frames if MAC SA misses,
#                         and frames are not 802.1X special frames
#                   [1] - drop frames that are not 802.1X special frames
#      e.g.: eth_802.1x_dm   = 0
#
#Item <<eth_802.1x_cm>>: The Port Map of 802.1X activated AMC Ports
#            List of AMC Ports
#            par_1: [alias] connection
#            par_.. [alias] connection
#     eth_802.1x_cm   =   AMC1/0, AMC2/0, AMC3/0, AMC4/0
#
#

eth_802.1x_ini  = 0





# ===  Quality of Service Configuration   ===
#
#Item <<eth_qos_cm>> QoS mapping
#         between: <port ID>-<VLAN Priority>-<Egress Queue>
#            par_1: - [alias] AMC Port
#            par_2: - Priority(0-7) at VLAN Tag of Ethernet Frame
#            par_3: - Egress Queue(0-3)
#

eth_qos_cm      =   AMC1/0,  00,  0
eth_qos_cm      =   AMC1/0,  01,  0
eth_qos_cm      =   AMC1/0,  02,  0
eth_qos_cm      =   AMC1/0,  03,  0
eth_qos_cm      =   AMC1/0,  04,  0
eth_qos_cm      =   AMC1/0,  05,  0
eth_qos_cm      =   AMC1/0,  06,  0
eth_qos_cm      =   AMC1/0,  07,  0
eth_qos_cm      =   AMC1/1,  00,  3
eth_qos_cm      =   AMC1/1,  01,  3
eth_qos_cm      =   AMC1/1,  02,  3
eth_qos_cm      =   AMC1/1,  03,  3
eth_qos_cm      =   AMC1/1,  04,  3
eth_qos_cm      =   AMC1/1,  05,  3
eth_qos_cm      =   AMC1/1,  06,  3
eth_qos_cm      =   AMC1/1,  07,  3
eth_qos_cm      =   AMC2/0,  00,  0
eth_qos_cm      =   AMC2/0,  01,  0
eth_qos_cm      =   AMC2/0,  02,  0
eth_qos_cm      =   AMC2/0,  03,  0
eth_qos_cm      =   AMC2/0,  04,  0
eth_qos_cm      =   AMC2/0,  05,  0
eth_qos_cm      =   AMC2/0,  06,  0
eth_qos_cm      =   AMC2/0,  07,  0
eth_qos_cm      =   AMC2/1,  00,  3
eth_qos_cm      =   AMC2/1,  01,  3
eth_qos_cm      =   AMC2/1,  02,  3
eth_qos_cm      =   AMC2/1,  03,  3
eth_qos_cm      =   AMC2/1,  04,  3
eth_qos_cm      =   AMC2/1,  05,  3
eth_qos_cm      =   AMC2/1,  06,  3
eth_qos_cm      =   AMC2/1,  07,  3
eth_qos_cm      =   AMC3/0,  00,  3
eth_qos_cm      =   AMC3/0,  01,  3
eth_qos_cm      =   AMC3/0,  02,  3
eth_qos_cm      =   AMC3/0,  03,  3
eth_qos_cm      =   AMC3/0,  04,  3
eth_qos_cm      =   AMC3/0,  05,  3
eth_qos_cm      =   AMC3/0,  06,  3
eth_qos_cm      =   AMC3/0,  07,  3
eth_qos_cm      =   AMC3/1,  00,  3
eth_qos_cm      =   AMC3/1,  01,  3
eth_qos_cm      =   AMC3/1,  02,  3
eth_qos_cm      =   AMC3/1,  03,  3
eth_qos_cm      =   AMC3/1,  04,  3
eth_qos_cm      =   AMC3/1,  05,  3
eth_qos_cm      =   AMC3/1,  06,  3
eth_qos_cm      =   AMC3/1,  07,  3
eth_qos_cm      =   AMC4/0,  00,  0
eth_qos_cm      =   AMC4/0,  01,  0
eth_qos_cm      =   AMC4/0,  02,  0
eth_qos_cm      =   AMC4/0,  03,  0
eth_qos_cm      =   AMC4/0,  04,  0
eth_qos_cm      =   AMC4/0,  05,  0
eth_qos_cm      =   AMC4/0,  06,  0
eth_qos_cm      =   AMC4/0,  07,  0
eth_qos_cm      =   AMC4/1,  00,  3
eth_qos_cm      =   AMC4/1,  01,  3
eth_qos_cm      =   AMC4/1,  02,  3
eth_qos_cm      =   AMC4/1,  03,  3
eth_qos_cm      =   AMC4/1,  04,  3
eth_qos_cm      =   AMC4/1,  05,  3
eth_qos_cm      =   AMC4/1,  06,  3
eth_qos_cm      =   AMC4/1,  07,  3
eth_qos_cm      =   AMC5/0,  00,  3
eth_qos_cm      =   AMC5/0,  01,  3
eth_qos_cm      =   AMC5/0,  02,  3
eth_qos_cm      =   AMC5/0,  03,  3
eth_qos_cm      =   AMC5/0,  04,  3
eth_qos_cm      =   AMC5/0,  05,  3
eth_qos_cm      =   AMC5/0,  06,  3
eth_qos_cm      =   AMC5/0,  07,  3
eth_qos_cm      =   AMC5/1,  00,  3
eth_qos_cm      =   AMC5/1,  01,  3
eth_qos_cm      =   AMC5/1,  02,  3
eth_qos_cm      =   AMC5/1,  03,  3
eth_qos_cm      =   AMC5/1,  04,  3
eth_qos_cm      =   AMC5/1,  05,  3
eth_qos_cm      =   AMC5/1,  06,  3
eth_qos_cm      =   AMC5/1,  07,  3
eth_qos_cm      =   AMC6/0,  00,  3
eth_qos_cm      =   AMC6/0,  01,  3
eth_qos_cm      =   AMC6/0,  02,  3
eth_qos_cm      =   AMC6/0,  03,  3
eth_qos_cm      =   AMC6/0,  04,  3
eth_qos_cm      =   AMC6/0,  05,  3
eth_qos_cm      =   AMC6/0,  06,  3
eth_qos_cm      =   AMC6/0,  07,  3
eth_qos_cm      =   AMC6/1,  00,  0
eth_qos_cm      =   AMC6/1,  01,  0
eth_qos_cm      =   AMC6/1,  02,  0
eth_qos_cm      =   AMC6/1,  03,  0
eth_qos_cm      =   AMC6/1,  04,  0
eth_qos_cm      =   AMC6/1,  05,  0
eth_qos_cm      =   AMC6/1,  06,  0
eth_qos_cm      =   AMC6/1,  07,  0
eth_qos_cm      =   FRT_1,  00,  0
eth_qos_cm      =   FRT_1,  01,  0
eth_qos_cm      =   FRT_1,  02,  0
eth_qos_cm      =   FRT_1,  03,  0
eth_qos_cm      =   FRT_1,  04,  0
eth_qos_cm      =   FRT_1,  05,  0
eth_qos_cm      =   FRT_1,  06,  0
eth_qos_cm      =   FRT_1,  07,  0
eth_qos_cm      =   FRT_2,  00,  0
eth_qos_cm      =   FRT_2,  01,  0
eth_qos_cm      =   FRT_2,  02,  0
eth_qos_cm      =   FRT_2,  03,  0
eth_qos_cm      =   FRT_2,  04,  0
eth_qos_cm      =   FRT_2,  05,  0
eth_qos_cm      =   FRT_2,  06,  0
eth_qos_cm      =   FRT_2,  07,  0
eth_qos_cm      =   UPDC_B,  00,  0
eth_qos_cm      =   UPDC_B,  01,  0
eth_qos_cm      =   UPDC_B,  02,  0
eth_qos_cm      =   UPDC_B,  03,  0
eth_qos_cm      =   UPDC_B,  04,  0
eth_qos_cm      =   UPDC_B,  05,  0
eth_qos_cm      =   UPDC_B,  06,  0
eth_qos_cm      =   UPDC_B,  07,  0
eth_qos_cm      =   RTM,  00,  0
eth_qos_cm      =   RTM,  01,  0
eth_qos_cm      =   RTM,  02,  0
eth_qos_cm      =   RTM,  03,  0
eth_qos_cm      =   RTM,  04,  0
eth_qos_cm      =   RTM,  05,  0
eth_qos_cm      =   RTM,  06,  0
eth_qos_cm      =   RTM,  07,  0
eth_qos_cm      =   CPU_1,  00,  0
eth_qos_cm      =   CPU_1,  01,  0
eth_qos_cm      =   CPU_1,  02,  0
eth_qos_cm      =   CPU_1,  03,  0
eth_qos_cm      =   CPU_1,  04,  0
eth_qos_cm      =   CPU_1,  05,  0
eth_qos_cm      =   CPU_1,  06,  0
eth_qos_cm      =   CPU_1,  07,  0





# ===  802.1p Quality of Service Configuration   ===
#
#Item <<eth_802.1p_ini>>: 802.1p Protocol state
#             par_1: [0] - deactivated
#                    [1] - activated
#
#
#Item <<eth_802.1p_cm>>: The Port Map of 802.1p activated Ports
#            List of AMC Ports
#            par_(1 ..n): [alias 1], .., [alias n]
#     e.g.: eth_802.1p_cm   =   AMC1/0, AMC2/0
#

eth_802.1p_ini  = 0





# ===   Port Mirroring Configuration   ===
#
#Item <<eth_mirr_ini>>:Port Mirroring state
#            par_1: [0] - deactivated
#                   [1] - activated
#
#
#Item <<eth_mirr_capt>>: Capture Port
#            par_1: [alias] - Capture Port
#     e.g.: eth_mirr_capt   =   FRT_2
#
#
#Item <<eth_mirr_icm>>: Ingress Port Map of Port Mirroring
#            par_(1-..): Ingress Mirror Maps (List of AMC Ports)
#            par_(1 ..n): [alias 1], .., [alias n]
#     e.g: eth_mirr_icm    =   AMC1/0, AMC2/0
#
#
#Item <<eth_mirr_ecm>>: Egress Port Map of Port Mirroring
#            par_(1-..): ): Egress Mirror Maps (List of AMC Ports)
#            par_(1 ..n): [alias 1], .., [alias n]
#     e.g: eth_mirr_ecm    =   AMC1/0, AMC4/0
#

eth_mirr_ini    = 0





# ===   Jumbo Configuration   ===
#
#Item <<eth_jumbo_ini>>:Port Mirroring state
#            par_1: [0] - deactivated
#                   [1] - activated
#
#
#Item <<eth_jumbo_fr_s>>: Egress Port Map of Port Mirroring
#            par_1: [alias]    AMC Port
#
#            par_2: [0] - OFF (normal frame size)
#                   [9] -  9K Jumbo frames
#     e.g.: eth_jumbo_fr_s  =   AMC2/0,  09
#

eth_jumbo_ini   = 0





# ===   Link Aggregation Configuration   ===
#
#Item <<eth_lag_ini>>:Link Aggregation initialization state
#            par_1: [0] - enabled
#                   [1] - disabled
#
#Item <<eth_lag_hash>>: Mask of member-Ports assigned to the aggregation group
#            par_1: [0] - DA^SA
#                   [1] - DA
#                   [2] - SA
#
#Item <<eth_lag_gr_cm>>: MAP of AMC Ports assigned to the aggregation group
#            par_1 [1-4]: Aggregation group ID
#            par_(2-n) : [alias 1], .., [alias n]   List of AMC Ports)
#     e.g: eth_lag_gr_cm    =  0,  AMC1/0, AMC2/0
#
#

eth_lag_ini     =    0





# ===   BPDU Traffic Filtering   ===
#
#Item <<eth_txfilt_ini>>:BPDU Traffic Filtering initialization state
#     par_1: [0] - enabled
#            [1] - disabled
#
#Item <<eth_txfilt_cm>>: BPDU Traffic Filtering Connection Map
#            par_(1-..): BPDU Traffic Maps (List of AMC Ports)
#            par_(1 ..n): [alias 1], .., [alias n]
#     e.g: eth_txfilt_cm    =   AMC1/0, FRT_2
#

eth_txfilt_ini  =    0





# ===   Inteface mode SGMII/SerDes   ===
#
#
#Item <<eth_sgmii_imode>>: Inteface mode on particular switch port
#            par_1: [alias]      AMC Port
#            par_2: [iff_mode]   Interface mode
#                         [serdes] - SerDes mode
#                         [sgmii]  - SGMII mode
#                         [auto]   - autodetection of mode
#

eth_sgmii_imode =   AMC1/0, serdes
eth_sgmii_imode =   AMC1/1, serdes
eth_sgmii_imode =   AMC2/0, serdes
eth_sgmii_imode =   AMC2/1, serdes
eth_sgmii_imode =   AMC3/0, serdes
eth_sgmii_imode =   AMC3/1, serdes
eth_sgmii_imode =   AMC4/0, serdes
eth_sgmii_imode =   AMC4/1, serdes
eth_sgmii_imode =   AMC5/0, serdes
eth_sgmii_imode =   AMC5/1, serdes
eth_sgmii_imode =   AMC6/0, serdes
eth_sgmii_imode =   AMC6/1, serdes





# ===   Connection Enable/Disable configuration   ===
#
#Item <<eth_enconn_map>>: list of connections that are enabled (are set to "administrative up")
#     e.g eth_enconn_map =AMC1/0, AMC1/1, AMC2/0, AMC2/1, AMC3/0
#
#If the configuration item is not present, the default port configuration has to applied
#automatically. This default port configuration suppresses the Ethernet loop via front GbE ports
#

eth_enconn_map =AMC1/0, AMC2/0, AMC3/0, AMC4/0, AMC5/0, AMC6/0, FRT_1, UPDC_B, CPU_1




#############################################################################
###           Clock Module configuration for NAT-MCH                      ###
#############################################################################

#
# ===  device location identifier  ===
#

mch_id = 0
mez_id = 1
inst_id = 0


#
# Item <<clk_pcb_maj>>: Clock for Physics PCB major version
# Item <<clk_pcb_min>>: Clock for Physics PCB minor version
#
# Syntax: clk_pcb_maj = maj_ver
# Syntax: clk_pcb_min = min_ver
#
# Params: maj_ver: major PCB version
# Params: min_ver: minor PCB version
#

clk_pcb_maj  =  1
clk_pcb_min  =  2


#
# Item <<clk_phys_out>>: clock output configuration
#
# Syntax: clk_phys_out = dst, src
#
# NOTE: For optimal jitter performance unused inputs should be configured as
#       outputs driving a signal with minimum signal transitions!
#
# HCSL buffer detected
# - any source for CLK 3 output other then 0 will enable output of HCSL buffer
#
# Params: dst: destination clock identifier
#                1 -  CLK1 AMC  1
#                2 -  CLK1 AMC  2
#                3 -  CLK1 AMC  3
#                4 -  CLK1 AMC  4
#                5 -  CLK1 AMC  5
#                6 -  CLK1 AMC  6
#                7 -  CLK1 AMC  7
#                8 -  CLK1 AMC  8
#                9 -  CLK1 AMC  9
#               10 -  CLK1 AMC 10
#               11 -  CLK1 AMC 11
#               12 -  CLK1 AMC 12
#               13 -  INTER-MUX 1 PORT 1
#               14 -  INTER-MUX 1 PORT 2
#               15 -  INTER-MUX 1 PORT 3
#               16 -  FPGA MUX 1
#               17 -  CLK2 AMC  1
#               18 -  CLK2 AMC  2
#               19 -  CLK2 AMC  3
#               20 -  CLK2 AMC  4
#               21 -  CLK2 AMC  5
#               22 -  CLK2 AMC  6
#               23 -  CLK2 AMC  7
#               24 -  CLK2 AMC  8
#               25 -  CLK2 AMC  9
#               26 -  CLK2 AMC 10
#               27 -  CLK2 AMC 11
#               28 -  CLK2 AMC 12
#               29 -  INTER-MUX 2 PORT 1
#               30 -  INTER-MUX 2 PORT 2
#               31 -  INTER-MUX 2 PORT 3
#               32 -  FPGA MUX 2
#               33 -  CLK3 AMC  1
#               34 -  CLK3 AMC  2
#               35 -  CLK3 AMC  3
#               36 -  CLK3 AMC  4
#               37 -  CLK3 AMC  5
#               38 -  CLK3 AMC  6
#               39 -  CLK3 AMC  7
#               40 -  CLK3 AMC  8
#               41 -  CLK3 AMC  9
#               42 -  CLK3 AMC 10
#               43 -  CLK3 AMC 11
#               44 -  CLK3 AMC 12
#               48 -  EXT single ended 2 (OUTPUT SMA 1)
#               50 -  EXT single ended 4 (OUTPUT SMA 2)
#
# Params: src: source clock identifier
#                0 -  disabled
#                1 -  CLK1 AMC  1
#                2 -  CLK1 AMC  2
#                3 -  CLK1 AMC  3
#                4 -  CLK1 AMC  4
#                5 -  CLK1 AMC  5
#                6 -  CLK1 AMC  6
#                7 -  CLK1 AMC  7
#                8 -  CLK1 AMC  8
#                9 -  CLK1 AMC  9
#               10 -  CLK1 AMC 10
#               11 -  CLK1 AMC 11
#               12 -  CLK1 AMC 12
#               13 -  INTER-MUX 1 PORT 1
#               14 -  INTER-MUX 1 PORT 2
#               15 -  INTER-MUX 1 PORT 3
#               16 -  FPGA MUX 1
#               17 -  CLK2 AMC  1
#               18 -  CLK2 AMC  2
#               19 -  CLK2 AMC  3
#               20 -  CLK2 AMC  4
#               21 -  CLK2 AMC  5
#               22 -  CLK2 AMC  6
#               23 -  CLK2 AMC  7
#               24 -  CLK2 AMC  8
#               25 -  CLK2 AMC  9
#               26 -  CLK2 AMC 10
#               27 -  CLK2 AMC 11
#               28 -  CLK2 AMC 12
#               35 -  EXT single ended 1 (INPUT  SMA 1)
#               37 -  EXT single ended 3 (INPUT  SMA 2)
#               41 -  100MHz OSC (only with HCSL option)
#

clk_phys_out =  1,  0
clk_phys_out =  2,  0
clk_phys_out =  3,  0
clk_phys_out =  4,  0
clk_phys_out =  5,  0
clk_phys_out =  6,  0
clk_phys_out =  7,  0
clk_phys_out =  8,  0
clk_phys_out =  9,  0
clk_phys_out = 10,  0
clk_phys_out = 11,  0
clk_phys_out = 12,  0
clk_phys_out = 13,  0
clk_phys_out = 14,  0
clk_phys_out = 15,  0
clk_phys_out = 16,  0
clk_phys_out = 17,  0
clk_phys_out = 18,  0
clk_phys_out = 19,  0
clk_phys_out = 20,  0
clk_phys_out = 21,  0
clk_phys_out = 22,  0
clk_phys_out = 23,  0
clk_phys_out = 24,  0
clk_phys_out = 25,  0
clk_phys_out = 26,  0
clk_phys_out = 27,  0
clk_phys_out = 28,  0
clk_phys_out = 29,  0
clk_phys_out = 30,  0
clk_phys_out = 31,  0
clk_phys_out = 32,  0
clk_phys_out = 33,  0
clk_phys_out = 34,  1
clk_phys_out = 35,  0
clk_phys_out = 36,  0
clk_phys_out = 37,  0
clk_phys_out = 38,  0
clk_phys_out = 39,  0
clk_phys_out = 40,  1
clk_phys_out = 41,  0
clk_phys_out = 42,  0
clk_phys_out = 43,  0
clk_phys_out = 44,  0
clk_phys_out = 48,  0
clk_phys_out = 50,  0


#
# Item <<clk_phys_termination>>: clock termination configuration
#
# Syntax: clk_phys_termination = dst, termination
#
# Params: dst: clock identifier
#                1 -  CLK1 AMC  1
#                2 -  CLK1 AMC  2
#                3 -  CLK1 AMC  3
#                4 -  CLK1 AMC  4
#                5 -  CLK1 AMC  5
#                6 -  CLK1 AMC  6
#                7 -  CLK1 AMC  7
#                8 -  CLK1 AMC  8
#                9 -  CLK1 AMC  9
#               10 -  CLK1 AMC 10
#               11 -  CLK1 AMC 11
#               12 -  CLK1 AMC 12
#               13 -  INTER-MUX 1 PORT 1
#               14 -  INTER-MUX 1 PORT 2
#               15 -  INTER-MUX 1 PORT 3
#               16 -  FPGA MUX 1
#               17 -  CLK2 AMC  1
#               18 -  CLK2 AMC  2
#               19 -  CLK2 AMC  3
#               20 -  CLK2 AMC  4
#               21 -  CLK2 AMC  5
#               22 -  CLK2 AMC  6
#               23 -  CLK2 AMC  7
#               24 -  CLK2 AMC  8
#               25 -  CLK2 AMC  9
#               26 -  CLK2 AMC 10
#               27 -  CLK2 AMC 11
#               28 -  CLK2 AMC 12
#               29 -  INTER-MUX 2 PORT 1
#               30 -  INTER-MUX 2 PORT 2
#               31 -  INTER-MUX 2 PORT 3
#               32 -  FPGA MUX 2
#
# Params: termination: enable/disable 100 R termination in multiplexer
#

clk_phys_termination =  1,  0
clk_phys_termination =  2,  0
clk_phys_termination =  3,  0
clk_phys_termination =  4,  0
clk_phys_termination =  5,  0
clk_phys_termination =  6,  0
clk_phys_termination =  7,  0
clk_phys_termination =  8,  0
clk_phys_termination =  9,  0
clk_phys_termination = 10,  0
clk_phys_termination = 11,  0
clk_phys_termination = 12,  0
clk_phys_termination = 13,  0
clk_phys_termination = 14,  0
clk_phys_termination = 15,  0
clk_phys_termination = 16,  0
clk_phys_termination = 17,  0
clk_phys_termination = 18,  0
clk_phys_termination = 19,  0
clk_phys_termination = 20,  0
clk_phys_termination = 21,  0
clk_phys_termination = 22,  0
clk_phys_termination = 23,  0
clk_phys_termination = 24,  0
clk_phys_termination = 25,  0
clk_phys_termination = 26,  0
clk_phys_termination = 27,  0
clk_phys_termination = 28,  0
clk_phys_termination = 29,  0
clk_phys_termination = 30,  0
clk_phys_termination = 31,  0
clk_phys_termination = 32,  0


#
# Item <<clk_wreg>>: write clock module register
#
# Syntax: clk_wreg = offs, value
#
# Params: offs: register offset
#         value: value to write
#


#
# Item <<clk_orreg>>: OR value to clock module register
#
# Syntax: clk_orreg = offs, value
#
# Params: offs: register offset
#         value: value to OR with current register value
#


#
# Item <<clk_andreg>>: AND value with clock module register
#
# Syntax: clk_andreg = offs, value
#
# Params: offs: register offset
#         value: value to AND with current register value
#



#
# Item <<clk_wblk>>: write block in clock module
#
# Syntax: clk_wblk = inst, len, data[0], data[1], ..., data[len - 1]
#
# Params: inst: addressed instance on clock module
#         len: number of bytes to write
#         data[n]: n-th data byte to write
#



#############################################################################
###           PCIe Module configuration for NAT-MCH                       ###
#############################################################################

#
# ===  device location identifier  ===
#

mch_id = 0
mez_id = 2
inst_id = 0


#
# Item <<pcie_pcb_maj>>: PCIe PCB major version
# Item <<pcie_pcb_min>>: PCIe PCB minor version
#
# Syntax: pcie_pcb_maj = maj_ver
# Syntax: pcie_pcb_min = min_ver
#
# Params: maj_ver: major PCB version
# Params: min_ver: minor PCB version
#

pcie_pcb_maj  =  1
pcie_pcb_min  =  1


#
# Item <<pcie_vs_cfg>>: initializes a Virtual Switch of the PCIe switch
#
# Syntax: pcie_vs_cfg = vs_id, up_amc, nt_up_amc, ds_amc_list
#
# Params: vs_id:       Virtual Switch Id (VS_0, VS_1,...VS_3)
#         up_amc:      Upstream PCIe device name
#         nt_up_amc:   NT-Upstream PCIe device name (only for VS_0 for all others only NONE) or NONE for none
#         ds_amc_list: Downstream PCIe device name
#
# Note: The possibility of choosing one of the following PCIe device naming
#       depends of the HUB-PCIe-x module and the backplane connection that
#       are used in the system!
#
#                       NONE    - none
#                       AMC1_4  - AMC1,  port 4..7
#                       AMC2_4  - AMC2,  port 4..7
#                       AMC3_4  - AMC3,  port 4..7
#                       AMC4_4  - AMC4,  port 4..7
#                       AMC5_4  - AMC5,  port 4..7
#                       AMC6_4  - AMC6,  port 4..7
#                       AMC7_4  - AMC7,  port 4..7
#                       AMC8_4  - AMC8,  port 4..7
#                       AMC9_4  - AMC9,  port 4..7
#                       AMC10_4 - AMC10, port 4..7
#                       AMC11_4 - AMC11, port 4..7
#                       AMC12_4 - AMC12, port 4..7
#                       RTM_x16 - RTM,   only with HUB-PCIe-x80
#                       OPT1    - OPT1,  only with HUB-PCIe-x80 (assembly option)
#                       OPT2    - OPT2,  only with HUB-PCIe-x80 (assembly option)
#                       AMC1_8  - AMC1,  port 8..11
#                       AMC2_8  - AMC2,  port 8..11
#                       AMC3_8  - AMC3,  port 8..11
#                       AMC4_8  - AMC4,  port 8..11
#                       AMC5_8  - AMC5,  port 8..11
#                       AMC6_8  - AMC6,  port 8..11
#                       AMC7_8  - AMC7,  port 8..11
#                       AMC8_8  - AMC8,  port 8..11
#                       AMC9_8  - AMC9,  port 8..11
#                       AMC10_8 - AMC10, port 8..11
#                       AMC11_8 - AMC11, port 8..11
#                       AMC12_8 - AMC12, port 8..11
#


#
# Item <<pcie_lnk_width>>: Sets PCIe link width of a switch station
#
# Syntax: pcie_lnk_width = pcie_station, link_width
#
# Params: pcie_station: PCIe switch station 0, 1, 2...
#
#                 PCIE_ST_0
#                 PCIE_ST_1
#                 PCIE_ST_2
#                 PCIE_ST_3
#                 PCIE_ST_4
#
#         link_width:  link width
#
#                 NONE
#                 LW_X16
#                 LW_X8X8
#                 LW_X8X4X4
#                 LW_X4X4X4X4
#                 <NULL>
#


#
# Item <<pcie_lnk_speed_max>>: Reduces the maximum PCIe speed of a switch 
#      port that is connected to the related AMC port
#
# Syntax: pcie_lnk_speed_max = amc, speed
#
# Params: amc:    related AMC port
#
#                 AMC1_4  - AMC1,  port 4..7
#                 AMC2_4  - AMC2,  port 4..7
#                 AMC3_4  - AMC3,  port 4..7
#                 AMC4_4  - AMC4,  port 4..7
#                 AMC5_4  - AMC5,  port 4..7
#                 AMC6_4  - AMC6,  port 4..7
#                 AMC7_4  - AMC7,  port 4..7
#                 AMC8_4  - AMC8,  port 4..7
#                 AMC9_4  - AMC9,  port 4..7
#                 AMC10_4 - AMC10, port 4..7
#                 AMC11_4 - AMC11, port 4..7
#                 AMC12_4 - AMC12, port 4..7
#                 RTM_x16 - RTM,   only with HUB-PCIe-x80
#                 OPT1    - OPT1,  only with HUB-PCIe-x80 (assembly option)
#                 OPT2    - OPT2,  only with HUB-PCIe-x80 (assembly option)
#                 AMC1_8  - AMC1,  port 8..11
#                 AMC2_8  - AMC2,  port 8..11
#                 AMC3_8  - AMC3,  port 8..11
#                 AMC4_8  - AMC4,  port 8..11
#                 AMC5_8  - AMC5,  port 8..11
#                 AMC6_8  - AMC6,  port 8..11
#                 AMC7_8  - AMC7,  port 8..11
#                 AMC8_8  - AMC8,  port 8..11
#                 AMC9_8  - AMC9,  port 8..11
#                 AMC10_8 - AMC10, port 8..11
#                 AMC11_8 - AMC11, port 8..11
#                 AMC12_8 - AMC12, port 8..11
#
#         speed:  max. link speed
#                 LS_2_5GTs - 2.5   GT/s
#                 LS_5_0GTs - 5.0   GT/s
#                 LS_8_0GTs - 8.0   GT/s
#


#
# Item <<pcie_up_delay>>: set <upstream slot power up delay>
#
# Syntax: pcie_up_delay = value
#
# Params: value: upstream slot power up delay time in seconds (min. 5sec)
#


#
# Item <<pcie_amc_up_delay>>: set <PCIe hot plug delay for AMCs>
#
# Syntax: pcie_amc_up_delay = value
#
# Params: value: PCIe hot plug delay time for AMCs in seconds (default 0sec)
#


#
# Item <<pcie_spread>>: enable <100 MHz spread spectrum>
#
# Syntax: pcie_spread = value
#
# Params: value: 0 = disabled (default); 1 = enabled
#
# Note: SSC only selectable when no LOSC option assembled 
#       and HUB-PCIe-x48 PCB >= V2.0 or HUB-PCIe-x80!
#


#
# Item <<pcie_hot_plug>>: enable <hot plug support>
#
# Syntax: pcie_hot_plug = value
#
# Params: value: 0 = disabled (default); 1 = enabled
#


#
# Item <<pcie_ek_early>>: enable <PCIe early ekey (before payload)>
#
# Syntax: pcie_ek_early = value
#
# Params: value: 0 = disabled (default); 1 = enabled
#


#
# Item <<pcie_ssc_iso_rtm>>: enable <SSC isolation for RTM>
#
# Syntax: pcie_ssc_iso_rtm = value
#
# Params: value: 0 = disabled (default); 1 = enabled
#


#
# Item <<pcie_res_from_rtm>>: enable <allow reset propagation>
#
# Syntax: pcie_res_from_rtm = value
#
# Params: value: 0 = disabled (default); 1 = enabled
#



#############################################################################
###           AMC Module configuration for NAT-MCH                        ###
#############################################################################



#
# Item <<amc_pwr_on>>: initialize AMC pwr_on
#
# Syntax: amc_pwr_on = fru_id, current_max, t_delay
#
# Params: fru_id: amc fru id 5...30
#         current_max: maximum current consumption in 100mA steps
#         t_delay: pwr_on delay time in 1sec steps (max. 65535 sec)
#



#############################################################################
###           Watch dog timer configuration for NAT-MCH                   ###
#############################################################################



#
# Item <<wd_exception_reset>>: enable reset when an exception occurs
#
# Syntax: wd_exception_reset = value
#
# Params: value: = 0 disabled; > 0 enabled
#
wd_exception_reset = 0


#
# Item <<wd_task_lost_reset>>: enable reset when one important task is lost
#
# Syntax: wd_task_lost_reset = value
#
# Params: value: = 0 disabled; > 0 enabled
#
wd_task_lost_reset = 0


#
# Item <<wd_shutdown_after_reset>>: enable shutdown after reset
#
# Syntax: wd_shutdown_after_reset = value
#
# Params: value: = 0 disabled; > 0 enabled
#
wd_shutdown_after_reset = 0
